Phase change memory devices have recently been developed. The phase change memory device has a nonvolatile property of maintaining stored data when its power supply is interrupted. A unit cell of the phase change memory device uses a phase change material as a data storing medium. The phase change material has two stable states, namely, an amorphous state and a crystalline state, which is controlled by heat provided to the cell structure by an applied current. A generally-known phase change, or chalcogenide, material is a compound of Ge, Sb and Te, commonly referred to as a GST material (Ge—Sb—Te). Specifically, one type of GST material is Ge2Sb2Te5.
When the GST material is heated for a short time at a temperature close to a melting point of the material and is then quickly cooled or quenched, the GST material is in its amorphous state. If the GST is heated for a long time at a crystallization temperature lower than the melting point and slowly cooled, the GST is in its crystalline state. The amorphous GST has a higher specific resistance than the crystalline GST.
Therefore, whether the information stored in the phase change memory cell is logical ‘1’ or ‘0’ can be determined by sensing an amount of current flowing through the phase change material.
Joule heat is used as the heat supplied to the phase change material. That is, when the current is supplied to an electrode connected to the phase change material, Joule heat is generated from the electrode and supplied to the phase change material. The temperature of the heat supplied to the phase change material is dependent upon the amount of the supplied current.
FIG. 1 is a cross-sectional diagram illustrating the structure of a conventional phase change memory cell. Referring to FIG. 1, a lower insulating layer 102 is formed on a semiconductor substrate. An upper insulating layer 122 is formed on the lower insulating layer 102. A first contact hole 105 is formed through the lower insulating layer 102, and a second contact hole 125 is formed in the upper insulating layer 122. The second contact hole 125 contains a conductive upper or top contact plug 127 made of a conductive material such as tungsten (W), aluminum (Al) or copper (Cu). The first contact hole 105 contains a conductive lower or bottom contact plug and heater 113a made of a conductive material such as TiAlN, TiN, or like material.
A layer of chalcogenide GST phase change material 115 is formed in the upper insulating layer 122 on the lower insulating layer 102. A conductive upper electrode 119, made of a material such as TiN, TaN, WN or similar material, is formed on the top surface of the GST phase change material 115. The phase change material 115 is electrically connected at its bottom surface to the lower plug or heater 113a and is electrically connected at its top surface to the upper electrode 119 and the upper contact plug 127. A conductive metal pattern 129, made of a conductive material such as W, Al, Cu, or similar material, is connected to the upper contact plug 127 and the upper electrode 119.
When the memory cell is programmed, a current is applied to the structure between the metal pattern 129 and the bottom contact and heater 113 a. As the current passes through the heater 113a, the resulting heat affects the state of the GST material 115 in a programmable volume or region 117. Depending on the programming process applied, the GST material in the programmable volume 117 takes on a crystalline state or an amorphous state. For example, to program the programmable volume to the crystalline state, the GST material can be heated to approximately 150 degrees C. by passing a current of approximately 0.56 mA through the material and allowing it to cool for approximately 500 ns. For example, to program the programmable volume to the amorphous state, the GST material can be heated to approximately 620 degrees C. by passing a current of approximately 1.2 mA through the material and allowing it to cool for approximately 4-5 ns.
FIG. 2A contains a schematic diagram of the memory cell of FIG. 1, and FIG. 2B is an equivalent schematic circuit diagram of a circuit in which the memory cell of FIG. 1 is used. Referring to FIGS. 2A and 2B, current from a bit line BL passes through the upper electrode 119 and the GST phase change material 115 to program the programmable volume 117 to the desired state. The GST phase change material 115 is indicated as a variable resistance. A word line is used to control a transistor 121 to enable the programming process. Current through the heater 113a heats the GST phase change material 115 to program the programmable volume 117 to the desired state. In one example configuration, the memory cell is programmed to a logic 0 state when the programmable volume 117 is in the amorphous state and the memory cell is programmed to a logic 1 state when the programmable volume 117 is in the crystalline state.
The memory cell described above can save one of two possible states, namely, a logic 0 state or a logic 1 state. In general, it is beneficial to create a multi-bit memory cell which can store one of more than two possible states to increase the data storage capacity of the memory. A multi-bit PRAM has been developed which uses hybrid states of the programmable volume to store more than one bit of information in a cell. In general, the programmable volume can be programmed to one of three possible states. In a first state, referred to as a fully reset state, the entire programmable volume is programmed to the amorphous state. In a second state, referred to as a fully set state, the entire programmable volume is programmed to the crystalline state. In a third state, part of the programmable volume is programmed to the crystalline state, and another part of the programmable volume is programmed to the amorphous state.
In this type of hybrid device, the volume fraction X of the programmable volume, i.e., the fraction of the programmable volume in the amorphous state, is controlled by controlling the magnitude of the programming current and/or the quenching time used after the programming current is removed. In general, the volume fraction X is a number between 0 and 1. In the fully reset state, X=1, and, in the fully set state, X=0. In the hybrid or mixed state, X is between 0 and 1, i.e., 0<X<1. Hence, theoretically, the hybrid memory cell can store three possible values. In practice, however, this type of device is very difficult to program. The volume fraction cannot be accurately controlled through the programming process, resulting in very high programming error and, as a result, very low programming reliability.